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About The Processor

uProcessor Design

This is a 6 stage RISC-V 32 IM built originally to form a SoC with OpenPiton and to be optimized for Cryptography by connecting a specific IP.

  • In order RV32IM
  • Use scoreboard to stall in every hazard (most simple fix)
  • OpenPiton Integration (to leverage Caches and Atomic Operations)
  • Privileged ISA
  • Crypto IP
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superscalar RV32M

RISCV 32 bit core with full I and M extensions support.

Simple architecture

Hazards are stalled 6 pipelines .. Cacheless architecture with daptive memory interface.

Linux capable

Has full privileged ISA support Can run full linux if integrated with an MMU.

Test Verified

ٍTested Using:- compliance tests.. Piton integration tests.. Uvm randomly generated tests.

Top Speed

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Secure Via Encryption

Encryption:- Aes cistom instructions .. 128 bit key support.

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